It is a board to inspect packaged SoC/SIP IC chips, serving as the medium between Tester and IC Chip. The recent trend is a rising clock speed, a faster rising time, a lowering operation voltage, and an increasing operation current. As a result, to minimize signal, power, and ground noises which are caused by impedance mismatch, coupling, frequency defendant loss, and bandwidth restriction that occur in test board’s Trace and Via Hole, and Cap, Res, and RLY, our company makes an effort to introduce Signal Integrity (SI) and Power Integrity (PI) Simulation to test board design.